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? copyright 2001 cirrus logic (all rights reserved) july ?01 ds506pp1 1 p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com high-performance, low-power system on chip with sdram and enhanced digital audio interface ep7311 data sheet overview block diagram features (cont.) (cont.) arm720t processor ?arm7tdmi cpu ? 8 kb of four-way set-associative cache ? mmu with 64-entry tlb ? thumb code support enabled ultra low power ? 90 mw at 74 mhz typical ? 30 mw at 18 mhz typical ? 10 mw in the idle state ? <1 mw in the standby state 48 kb of on-chip sram maverickkey ? ids ? 32-bit unique id can be used for sdmi compliance ? 128-bit random id dynamically programmable clock speeds of 18, 36, 49, and 74 mhz lcd controller boot rom maverickkey tm arm7tdmi cpu core mmu 8 kb cache write buffer internal data bus epb bus memory controller sdram i/f sram i/f on-chip sram 48 kb ice-jtag clocks & timers keypad& touch screen i/f interrupts, pwm & gpio bus bridge (2) uarts w/ irda power management serial interface multimedia codec port arm720t memory and storage user interface serial ports the maverick ? ep7311 is designed for ultra-low-power applications such as pdas, smart cellular phones, and industrial hand held information appliances. the core- logic functionality of the device is built around an arm720t processor with 8 kb of four-way set- associative unified cache and a write buffer. incorporated into the arm720t is an enhanced memory management unit (mmu) which allows for support of sophisticated operating systems like linux ? .
2 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip features (cont) lcd controller ? interfaces directly to a single-scan panel monochrome stn lcd ? interfaces to a single-scan panel color stn lcd with minimal external glue logic full jtag boundary scan and embedded ice ? support integrated peripheral interfaces ? 32-bit sdram interface up to 2 external banks ? 8/32/16-bit sram/flash/rom interface ? multimedia codec port ? two synchronous serial interfaces (ssi1, ssi2) ? codec sound interface ? 8 8keypad scanner ? 27 general purpose input/output pins ? dedicated led flasher pin from the rtc internal peripherals ? two 16550 compatible uarts ? irda interface ? tw o pw m in terfaces ? real-time clock ? two general purpose 16-bit timers ? interrupt controller ? boot rom package ? 208-pin lqfp ? 256-ball pbga ? 204-ball tfbga the fully static ep7311 is optimized for low power dissipation and is fabricated on a 0.25 micron cmos process development kits ? edb7312: development kit with color stn lcd on board. ? edb7312-lw: edb7312 with lynuxworks ? bluecat linux tools and software for windows host (free 30 day bluecat support from lynuxworks). ? edb7312-ll: edb7312 with lynuxworks ? bluecat linux tools and software for linux host (free 30 day bluecat support from lynuxworks). note: * bluecat available separately through lynuxworks only. * use the edb7312 development kit for all the ep73xx devices. overview (cont.) the ep7311 is designed for low-power operation. its core operates at only 2.5 v, while its i/o has an operation range of 2.5 v ? 3.3 v. the device has three basic power states: operating, idle and standby. one of its notable features is maverickkey unique ids. these are factory programmed ids in response to the growing concern over secure web content and commerce. with internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. the maverickkey unique ids consist of two registers, one 32-bit series register and one random 128- bit register that may be used by an oem for an authentication mechanism. simply by adding desired memory and peripherals to the highly integrated ep7311 completes a low-power system solution. all necessary interface logic is integrated on- chip. contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product information de- scribes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensur e that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other r ights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or trade secrets. no part of this publicati on may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any m eans (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may b e copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior writ ten consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of ci rrus logic, inc. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective ow ners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http ://www.cirrus.com.
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 3 ep7311 high-performance, low-power system on chip processor core - arm720t the ep7311 incorporates an arm 32-bit risc microcontroller that controls a wide range of on-chip peripherals. the processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. key features include: arm (32-bit) and thumb (16-bit compressed) instruction sets enhanced mmu for microsoft windows ce and other operating systems 8 kb of 4-way set-associative cache. translation look aside buffers with 64 translated entries power management the ep7311 is designed for ultra-low-power operation. its core operates at only 2.5 v, while its i/o has an operation range of 2.5 v ? 3.3 v allowing the device to achieve a performance level equivalent to 60 mips. the device has three basic power states: operating ? this state is the full performance state. all the clocks and peripheral logic are enabled. idle ? this state is the same as the operating state, except the cpu clock is halted while waiting for an event such as a key press. standby ? this state is equivalent to the computer being switched off (no display), and the main oscillator shut down. an event such as a key press can wake-up the processor. maverickkey ? unique id maverickkey unique hardware programmed ids are a solution to the growing concern over secure web content and commerce. with internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. the maverickkey unique ids provide oems with a method of utilizing specific hardware ids such as those assigned for sdmi (secure digital music initiative) or any other authentication mechanism. both a specific 32-bit id as well as a 128-bit random id is programmed into the ep7311 through the use of laser probing technology. these ids can then be used to match secure copyrighted content with the id of the target device the ep7311 is powering, and then deliver the copyrighted information over a secure connection. in addition, secure transactions can benefit by also matching device ids to server ids. maverickkey ids provide a level of hardware security required for today ? s internet appliances. memory interfaces there are two main external memory interfaces. the first one is the rom/sram/flash-style interface that has programmable wait-state timings and includes burst- mode capability, with six chip selects decoding six 256 mb sections of addressable space. for maximum flexibility, each bank can be specified to be 8-, 16-, or 32- bits wide. this allows the use of 8-bit-wide boot rom options to minimize overall system cost. the on-chip boot rom can be used in product manufacturing to serially download system code into system flash memory. to further minimize system memory requirements and cost, the arm thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industry- leading code density. note: pins are multiplexed. see table s on page 8 for more information. pin mnemonic i/o pin description batok i battery ok input nextpwr i external power supply sense input npwrfl i power fail sense input nbatchg i battery changed sense input table a. power management pin assignments pin mnemonic i/o pin description ncs[5:0] o chip select out a[27:0] o address output d[31:0] i/o data i/o nmoe/nsdcas (note) o rom expansion op enable nmwe/nsdwe (note) o rom expansion write enable halfword o halfword access select output word o word access select output write/nsdras (note) o transfer direction table b. static memory interface pin assignments
4 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip the second is the programmable 16- or 32-bit-wide sdram interface that allows direct connection of up to two banks of sdram, totaling 512 mb. to assure the lowest possible power consumption, the ep7311 supports self-refresh sdrams, which are placed in a low-power state by the device when it enters the low- power standby state. note: 1. pins a[27:13] map to dra[0:14] respectively. (i.e. a[27}/dra[0}, a[26}/dra[1], etc.) this is to balance the load for large memory systems. 2. pins are multiplexed. see table s on page 8 for more information. digital audio capability the ep7311 uses its powerful 32-bit risc processing engine to implement audio decompression algorithms in software. the nature of the on-board risc processor, and the availability of efficient c-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the ep7311 universal asynchronous receiver/transmitters (uarts) the ep7311 includes two 16550-type uarts for rs-232 serial communications, both of which have two 16-byte fifos for receiving and transmitting data. the uarts support bit rates up to 115.2 kbps. an irda sir protocol encoder/decoder can be optionally switched into the rx/tx signals to/from uart 1 to enable these signals to drive an infrared communication interface directly. multimedia codec port (mcp) the multimedia codec port provides access to an audio codec, a telecom codec, a touchscreen interface, four general purpose analog-to-digital converter inputs, and ten programmable digital i/o lines. note: see table r on page 8 for information on pin multiplexes. pin mnemonic i/o pin description sdclk o sdram clock output sdcke o sdram clock enable output nsdcs[1:0] o sdram chip select out write/nsdras (note 2) o sdram ras signal output nmoe/nsdcas (note 2) o sdram cas control signal nmwe/nsdwe (note 2) o sdram write enable control signal a[27:15]/dra[0:12] (note 1) o sdram address a[14:13]/dra[12:14] o sdram internal bank select pd[7:6]/sdqm[1:0] (note 2) i/o sdram byte lane mask sdqm[3:2] o sdram byte lane mask d[31:0] i/o data i/o table c. sdram interface pin assignments pin mnemonic i/o pin description txd[1] o uart 1 transmit rxd[1] i uart 1 receive cts i uart 1 clear to send dcd i uart 1 data carrier detect dsr i uart 1 data set ready txd[2] o uart 2 transmit rxd[2] i uart 2 receive leddrv o infrared led drive output phdin i photo diode input table d. universal asynchronous receiver/transmitters pin assignments pin mnemonic i/o pin description sibclk o serial bit clock sibdout o serial data out sibdin i serial data in sibsync o sample clock table e. mcp interface pin assignments
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 5 ep7311 high-performance, low-power system on chip codec interface the ep7311 includes an interface to telephony-type codecs for easy integration into voice-over-ip and other voice communications systems. the codec interface is multiplexed to the same pins as the mcp and ssi2. note: see table r on page 8 for information on pin multiplexes. ssi2 interface an additional spi/microwire1-compatible interface is available for both master and slave mode communications. the ssi2 unit shares the same pins as the mcp and codec interfaces through a multiplexer. synchronous clock speeds of up to 512 khz separate 16 entry tx and rx half-word wide fifos half empty/full interrupts for fifos separate rx and tx frame sync signals for asymmetric traffic note: see table r on page 8 for information on pin multiplexes. synchronous serial interface adc (ssi) interface: master mode only; spi and microwire1-compatible (128 kbps operation) selectable serial clock polarity lcd controller a dma address generator is provided that fetches video display data for the lcd controller from memory. the display frame buffer start address is programmable, allowing the lcd frame buffer to be in sdram, internal sram or external sram. interfaces directly to a single-scan panel monochrome stn lcd interfaces to a single-scan panel color stn lcd with minimal external glue logic panel width size is programmable from 32 to 1024 pixels in 16-pixel increments video frame buffer size programmable up to 128 kb bits per pixel of 1, 2, or 4 bits pin mnemonic i/o pin description pcmclk o serial bit clock pcmout o serial data out pcmin i serial data in pcmsync o frame sync table f. codec interface pin assignments pin mnemonic i/o pin description ssiclk i/o serial bit clock ssitxda o serial data out ssirxda i serial data in ssitxfr i/o transmit frame sync ssirxfr i/o receive frame sync table g. ssi2 interface pin assignments pin mnemonic i/o pin description adclk o ssi1 adc serial clock adcin i ssi1 adc serial input adcout o ssi1 adc serial output nadccs o ssi1 adc chip select smpclk o ssi1 adc sample clock table h. serial interface pin assignments pin mnemonic i/o pin description cl1 o lcd line clock cl2 o lcd pixel clock out dd[3:0] o lcd serial display data bus frm o lcd frame synchronization pulse m o lcd ac bias drive table i. lcd interface pin assignments
6 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip 64-keypad interface matrix keyboards and keypads can be easily read by the ep7311. a dedicated 8-bit column driver output generates strobes for each keyboard column signal. the pins of port a, when configured as inputs, can be selectively or ? ed together to provide a keyboard interrupt that is capable of waking the system from a standby or idle state. column outputs can be individually set high with the remaining bits left at high-impedance column outputs can be driven all-low, all-high, or all- high-impedance keyboard interrupt driven by or'ing together all port a bits keyboard interrupt can be used to wake up the system 8 8 keyboard matrix usable with no external logic, extra keys can be added with minimal glue logic interrupt controller when unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. when these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. the ep7311 interrupt controller has two interrupt types: interrupt request (irq) and fast interrupt request (fiq). the interrupt controller has the ability to control interrupts from 22 different fiq and irq sources. supports 22 interrupts from a variety of sources (such as uarts, ssi1, and key matrix.) routes interrupt sources to the arm720t ? s irq or fiq (fast irq) inputs five dedicated off-chip interrupt lines operate as level sensitive interrupts . note: pins are multiplexed. see table s on page 8 for more information. real-time clock the ep7311 contains a 32-bit real time clock (rtc) that can be written to and read from in the same manner as the timer counters. it also contains a 32-bit output match register which can be programmed to generate an interrupt. driven by an external 32.768 khz crystal oscillator pll and clocking processor and peripheral clocks operate from a single 3.6864 mhz crystal or external 13 mhz clock programmable clock speeds allow the peripheral bus to run at 18 mhz when the processor is set to 18 mhz and at 36 mhz when the processor is set to 36, 49 or 74 mhz pin mnemonic i/o pin description col[7:0] o keyboard scanner column drive table j. keypad interface pin assignments pin mnemonic i/o pin description neint[2:1] i external interrupt eint[3] i external interrupt nextfiq i external fast interrupt input nmedchg/nbrom (note) i media change interrupt input table k. interrupt controller pin assignments pin mnemonic pin description rtcin real-time clock oscillator input rtcout real-time clock oscillator output vddrtc real-time clock oscillator power vssrtc real-time clock oscillator ground table l. real-time clock pin assignments pin mnemonic pin description moscin main oscillator input moscout main oscillator output vddosc main oscillator power vssosc main oscillator ground table m. pll and clocking pin assignments
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 7 ep7311 high-performance, low-power system on chip dc-to-dc converter interface (pwm) provides two 96 khz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative dc to dc converter timers internal (rtc) timer two internal 16-bit programmable hardware count- down timers general purpose input/output (gpio) three 8-bit and one 3-bit gpio ports supports scanning keyboard matrix note: pins are multiplexed. see table s on page 8 for more information. hardware debug interface full jtag boundary scan and embedded ice ? support led flasher a dedicated led flasher module can be used to generate a low frequency signal on port d pin 0 for the purpose of blinking an led without cpu intervention. the led flasher feature is ideal as a visual annunciator in battery powered applications, such as a voice mail indicator on a portable phone or an appointment reminder on a pda. software adjustable flash period and duty cycle operates from 32 khz rtc clock will continue to flash in idle and standby states 4 ma drive current note: pins are multiplexed. see table s on page 8 for more information. internal boot rom the internal 128 byte boot rom facilitates download of saved code to the on-board sram/flash. packaging the ep7311 is available in a 208-pin lqfp package, 256- ball pbga package or a 204-ball tfbga package. pin mnemonic i/o pin description drive[1:0] i/o pwm drive output fb[1:0] i pwm feedback input table n. dc-to-dc converter interface pin assignments pin mnemonic i/o pin description pa[7:0] i gpio port a pb[7:0] i gpio port b pd[0]/ledflsh (note) i/o gpio port d pd[5:1] i/o gpio port d pd[7:6]/sdqm[1:0] (note) i/o gpio port d pe[1:0]/bootsel[1:0] (note) i gpio port e pe[2]/clksel (note) i gpio port e table o. general purpose input/output pin assignments pin mnemonic i/o pin description tclk i jtag clock tdi i jtag data input tdo o jtag data output ntrst i jtag async reset input tms i jtag mode select table p. hardware debug interface pin assignments pin mnemonic i/o pin description pd[0]/ledflsh (note) o led flasher driver table q. led flasher pin assignments
8 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip pin multiplexing the following table shows the pin multiplexing of the mcp, ssi2 and the codec. the selection between ssi2 and the codec is controlled by the state of the sersel bit in syscon2. the choice between the ssi2, codec, and the mcp is controlled by the mcpsel bit in syscon3 (see the ep73xx user ? s manual for more information). the following table shows the pins that have been multiplexed in the ep7311. pin mnemonic i/o mcp ssi2 codec ssiclk i/o sibclk ssiclk pcmclk ssitxda o sibdout ssitxda pcmout ssirxda i sibdin ssirxda pcmin ssitxfr i/o sibsync ssitxfr pcmsync ssirxfr i p/u ssirxfr p/u buz o table r. mcp/ssi2/codec pin multiplexing signal block signal block nmoe static memory nsdcas sdram nmwe static memory nsdwe sdram write static memory nsdras sdram a[27:15] static memory dra[0:12] sdram a[14:13] static memory dra[13:14] sdram pd[7:6] gpio sdqm[1:0] sdram run system configuration clken system configuration nmedchg interrupt controller nbrom boot rom select pd[0] gpio ledflsh led flasher pe[1:0] gpio bootsel[1:0] system configuration pe[2] gpio clksel system configuration table s. pin multiplexing
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 9 ep7311 high-performance, low-power system on chip system design as shown in system block diagram, simply adding desired memory and peripherals to the highly integrated ep7311 completes a low-power system solution. all necessary interface logic is integrated on-chip. figure 1. a maximum ep7311 based system note: a system can only use one of the following peripheral interfaces at any given time: ssi2,codec or mcp. lcd keyboard battery dc-to-dc converters adc digitizer ir led and photodiode 2 rs-232 transceivers additional i/o pc card controller pc card socket ncs[4] pb0 expclk dd[0-3] cl1 cl2 frm m d[0-31] a[0-27] col[0-7] pa[0-7] dc input nmoe write pb[0-7] pd[0-7] pe[0-2] npor npwrfl batok nextpwr nbatchg run wakeup ncs[0] ncs[1] drive[0-1] fb[0-1] ep7311 adcclk nadccs adcout adcin smpclk leddrv phdin rxd1/2 txd1/2 dsr cts dcd cs[n] word ncs[2] ncs[3] 16 flash 16 flash 1 6 flash external memory- mapped expansion buffers buffers and latches 16 flash power supply unit and comparators crystal codec/ssi2/ mcp ssiclk ssitxfr ssitxda ssirxda ssirxfr rtcin ledflsh crystal moscin 16 sdram 16 sdram 1 6 sdram 16 sdram sdcs[1] s dqm[0-3] sdcs[0] sdqm[0-3] sdras/ sdcas
10 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip electrical specifications absolute maximum ratings recommended operating conditions dc characteristics all characteristics are specified at v dd = 2.5 v and v ss = 0 v over an operating temperature of 0 c to +70 c for all frequencies of operation. the current consumption figures relate to typical conditions at 2.5 v, 18.432 mhz operation with the pll switched ? on. ? dc core, pll, and rtc supply voltage 2.9 v dc i/o supply voltage (pad ring) 3.6 v dc pad input current 10 ma/pin; 100 ma cumulative storage temperature, no power ? 40 c to +125 c dc core, pll, and rtc supply voltage 2.5 v 0.2 v dc i/o supply voltage (pad ring) 2.3 v - 3.6 v dc input / output voltage o ? i/o supply voltage operating temperature extended -20 c to +70 c; commercial 0 c to +70 c; industrial -40 c to +85 c symbol parameter min typ max unit conditions vih cmos input high voltage 0.65 v ddio v ddio + 0.3 v v ddio = 2.5 v vil cmos input low voltage -0.3 0.25 v ddio v v ddio = 2.5 v vt+ schmitt trigger positive going threshold 1.6 (typ) 2.0 v vt- schmitt trigger negative going threshold 0.8 1.2 (typ) v vhst schmitt trigger hysteresis 0.1 0.4 v vil to vih voh cmos output high voltage a output drive 1 a output drive 2 a v dd ? 0.2 2.5 2.5 v v v ioh = 0.1 ma ioh = 4 ma ioh = 12 ma vol cmos output low voltage a output drive 1 a output drive 2 a 0.3 0.5 0.5 v v v iol = ? 0.1 ma iol = ? 4ma iol = ? 12 ma iin input leakage current 1.0 a vin = v dd or gnd ioz bidirectional 3-state leakage current b c 25 100 a vout = v dd or gnd cin input capacitance 8 10.0 pf
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 11 ep7311 high-performance, low-power system on chip note: 1) all power dissipation values can be derived from taking the particular idd current and multiplying by 2.5 v. 2) the rtc of the ep7311 should be brought up at room temperature. this is required because the rtc osc will not function properly if it is brought up at ?40 c. once operational, it will continue to operate down to ?20 c extended and 0 c commercial. 3) a typical design will provide 3.3 v to the i/o supply (i.e., v dd io), and 2.5 v to the remaining logic. this is to allow the i/o to be compatible with 3.3 v powered external logic (i.e., 3.3 v sdrams). 4) pull-up current = 50 a typical at v dd = 3.3 v. cout output capacitance 8 10.0 pf ci/o transceiver capacitance 8 10.0 pf idd standby standby current consumption core, osc, rtc @2.5 v i/o @ 3.3 v tbd tbd 300 a only 32 khz oscillator running, cache disabled, all other i/o static, vih = v dd 0.1 v, vil = gnd 0.1 v idd idle idle current consumption core, osc, rtc @2.5 v i/o @ 2.5 v tbd tbd 4.2 ma both oscillators running, cpu static, cache disabled, lcd refresh active, vih = v dd 0.1 v, vil = gnd 0.1 v at 13 mhz idd operatin operating current consumption core, osc, rtc @2.5 v i/o @ 3.3 v tbd tbd ma all system active, running typical program, cache disabled, and lcd inactive v ddstandby standby supply voltage tbd v minimum standby voltage for state retention and rtc operation only a. see table t on page 29 . b. assumes buffer has no pull-up or pull-down resistors. c. the leakage value given assumes that the pin is configured as an input pin but is not currently being driven. symbol parameter min typ max unit conditions
12 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip timings timing diagram conventions this data sheet contains one or more timing diagrams. the following key explains the components used in these diagrams. any variations are clearly labelled when they occur. therefore, no additional meaning should be attached unless specifically stated. timing conditions unless specified otherwise, the following conditions are true for all timing measurements. all characteristics are specified at v dd = 2.3 - 2.7 v and v ss = 0 v over an operating temperature of 0 c to +70 c. those characteristics marked with a # will be significantly different for 13 mhz mode because the expclk is provided as an input rather than generated internally. these timings are estimated at present. the timing values are referenced to 1/2 v dd . clock high to low high/low to high bus change bus valid undefined/invalid valid bus to tristate bus/signal omission
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 13 ep7311 high-performance, low-power system on chip sdram interface figure 2 through figure 5 define the timings associated with all phases of the sdram. the following table contains the values for the timings of each of the sdram modes. parameter symbol min typ max unit sdclk rising edge to sdcs assert delay time t csa tbd 0 tbd ns sdclk rising edge to sdcs deassert delay time t csd tbd 0 tbd ns sdclk rising edge to sdras assert delay time t raa tbd 0 tbd ns sdclk rising edge to sdras deassert delay time t rad tbd 0 tbd ns sdclk rising edge to sdras invalid delay time t ranv tbd 0 tbd ns sdclk rising edge to sdcas assert delay time t caa tbd 0 tbd ns sdclk rising edge to sdcas deassert delay time t cad tbd 0 tbd ns sdclk rising edge to addr transition time t adv tbd 0 tbd ns sdclk rising edge to addr invalid delay time t adx tbd 0 tbd ns sdclk rising edge to sdmwe assert delay time t mwa tbd 0 tbd ns sdclk rising edge to sdmwe deassert delay time t mwd tbd 0 tbd ns data transition to sdclk rising edge time t das tbd - tbd ns sdclk rising edge to data transition hold time t dah tbd - tbd ns sdclk rising edge to data transition delay time t dad tbd - tbd ns
14 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip sdram load mode register cycle figure 2. sdram load mode register cycle timing measurement sdclk sdcs sdras sdcas addr data sdqm sdmwe t csa t raa t caa t mwa t adv t adx t rad t csd t cad t mwd
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 15 ep7311 high-performance, low-power system on chip sdram burst read cycle note: 1. timings are shown with cas latency = 2 2. depending on clock line loading, sdclk may be phase shifted to the right. figure 3. sdram burst read cycle timing measurement adras adcas sdclk sdcs sdras sdcas sdqm [0:3] addr data sdmwe d1 d4 d3 d2 t adv t adv t csd t csa t csa t caa t rad t csd t cad t raa t dah t das t dah t das t dah t das t dah t das t ranv
16 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip sdram burst write cycle figure 4. sdram burst write cycle timing measurement sdclk sdcs sdras sdcas sdqm addr data sdmwe 0 d1 adras adcas d4 d3 d2 t csa t raa t caa t csa t csd t rad t csd t cad t adv t dad t adv t dad t dad t dad t mwa t mwd
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 17 ep7311 high-performance, low-power system on chip sdram refresh cycle figure 5. sdram refresh cycle timing measurement sdclk sdcs sdras sdcas sdqm [3:0] sdmwe sdata addr t csa t raa t csd t rad t caa t cad
18 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip static memory figure 6 through figure 9 define the timings associated with all phases of the static memory. the following table contains the values for the timings of each of the static memory modes. parameter symbol min typ max unit expclk rising edge to ncs assert delay time t csd tbd 8 tbd ns expclk falling edge to ncs deassert hold time t csh tbd 4 tbd ns expclk rising edge to a assert delay time t ad tbd 4 tbd ns expclk falling edge to a deassert hold time t ah tbd 8 tbd ns expclk rising edge to nmwe assert delay time t mwd tbd 4 tbd ns expclk rising edge to nmwe deassert hold time t mwh tbd 4 tbd ns expclk falling edge to nmoe assert delay time t moed tbd 4 tbd ns expclk falling edge to nmoe deassert hold time t moeh tbd 4 tbd ns expclk falling edge to halfword deassert delay time t hwd tbd 4 tbd ns expclk falling edge to word assert delay time t wdd tbd 4 tbd ns expclk rising edge to data valid delay time t dv tbd 20 tbd ns expclk falling edge to data invalid delay time t dnv tbd 8 tbd ns data setup to expclk falling edge time t ds tbd - tbd ns expclk falling edge to data hold time t dh tbd - tbd ns expclk rising edge to write assert delay time t wrd tbd 8 tbd ns expready setup to expclk falling edge time t exs tbd - tbd ns expclk falling edge to expready hold time t exh tbd - tbd ns
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 19 ep7311 high-performance, low-power system on chip static memory single read cycle note: 1. the cycle time can be extended by integer multiples of the clock period (27 ns at 36 mhz, 54 ns at 18.432 mhz, and 77 ns at 13 mhz), by either driving exprdy low and/or by programming a number of wait states. exprdy is sampled on the falling edge of expclk before the data transfer. if low at this point, the transfer is delayed by one clock period where exprdy is sampled again. expclk need not be referenced when driving exprdy, but is shown for clarity. figure 6. static memory single read cycle timing measurement expclk ncs a nmwe half- word word d write nmoe t csd t ad t csh t moeh t dh t ds t hwd t wdd t wrd t moed exprdy t exh t exs
20 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip static memory single write cycle note: 1. the cycle time can be extended by integer multiples of the clock period (27 ns at 36 mhz, 54 ns at 18.432 mhz, and 77 ns at 13 mhz), by either driving exprdy low and/or by programming a number of wait states. exprdy is sampled on the falling edge of expclk before the data transfer. if low at this point, the transfer is delayed by one clock period where exprdy is sampled again. expclk need not be referenced when driving exprdy, but is shown for clarity. 2. zero wait states for sequential writes is not permitted for memory devices which use nmwe pin, as this cannot be driven with valid timing under zero wait state conditions. figure 7. static memory single write cycle timing measurement expclk ncs a nmwe half- word word d write t hwd t wdd t csd t ad t mwd t dv t mwh t csh nmoe exprdy t exh t exs
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 21 ep7311 high-performance, low-power system on chip static memory burst read cycle note: 1. four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). this is the maximum number of consecutive cycles that can be driven. the number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. the cycle time can be extended by integer multiples of the clock period (27 ns at 36 mhz, 54 ns at 18.432 mhz, and 77 ns at 13 mhz), by either driving exprdy low and/or by programming a number of wait states. exprdy is sampled on the falling edge of expclk before the data transfer. if low at this point, the transfer is delayed by one clock period where exprdy is sampled again. expclk need not be referenced when driving exprdy, but is shown for clarity. 3. consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential rom/expansion cycles. this improves performance so the sqaen bit should always be set where possible. figure 8. static memory burst read cycle timing measurement expclk ncs a nmoe half word word d nmwe exprdy write t csd t ad t ah t ah t ah t csh t moeh t moed t exs t exh t ds t dh t ds t ds t ds t dh t dh t dh t wrd t hwd t wdd
22 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip static memory burst write cycle note: 1. four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). this is the maximum number of consecutive cycles that can be driven. the number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. the cycle time can be extended by integer multiples of the clock period (27 ns at 36 mhz, 54 ns at 18.432 mhz, and 77 ns at 13 mhz), by either driving exprdy low and/or by programming a number of wait states. exprdy is sampled on the falling edge of expclk before the data transfer. if low at this point, the transfer is delayed by one clock period where exprdy is sampled again. expclk need not be referenced when driving exprdy, but is shown for clarity. 3. zero wait states for sequential writes is not permitted for memory devices which use nmwe pin, as this cannot be driven with valid timing under zero wait state conditions. figure 9. static memory burst write cycle timing measurement expclk ncs a nmoe half word word d nmwe exprdy write t csd t ad t mwd t mwh t mwd t mwd t mwd t mwh t mwh t mwh t ah t ah t ah t exs t exh t csh t dv t dv t dv t dnv t dnv t dnv t dv t hwd t wdd
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 23 ep7311 high-performance, low-power system on chip ssi1 interface parameter symbol min max unit adcclk falling edge to nadccss deassert delay time t cd tbd tbd ns adcin data setup to adcclk rising edge time t ins tbd tbd ns adcin data hold from adcclk rising edge time t inh tbd tbd ns adcclk falling edge to data valid delay time t ovd tbd tbd ns adcclk falling edge to data invalid delay time t od tbd tbd ns figure 10. ssi1 interface timing measurement adc clk nadc css adcin adc out t ins t inh t cd t od t ovd
24 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip ssi2 interface parameter symbol min max unit ssiclk period (slave mode) t clk_per 0 512 ns ssiclk high time t clk_high 925 1025 ns ssiclk low time t clk_low 925 1025 ns ssiclk rise/fall time t clkrf 7ns ssiclk rising edge to rx and/or tx frame sync high time t frd 528 ns ssiclk rising edge to rx and/or tx frame sync low time t fra 448 ns ssirxfr and/or ssitxfr period t fr_per 750 ns ssirxda setup to ssiclk falling edge time t rxs 30 ns ssirxda hold from ssiclk falling edge time t rxh 40 ns ssiclk rising edge to ssitxda data valid delay time t txd 80 ns ssitxda valid time t txv ns figure 11. ssi2 interface timing measurement ssi clk ssirxfr/ ssitxfr ssi txda ssi rxda d1 d7 d7 d2 d2 d1 d0 d0 t clk_per t clk_high t clk_low t frd t fr_per t rxs t txd t fra t rxh t clkrf t txv
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 25 ep7311 high-performance, low-power system on chip lcd interface parameter symbol min max unit cl[1] falling to cl[2] falling time t clk 200 6,950 ns lcd cl[2] low time t clk_low 80 3,475 ns lcd cl[2] high time t clk_high 80 3,475 ns cl[2] falling to cl[1] rising delay time t cl1d 025ns cl[1] falling to cl[2] rising delay time t cl2d 80 3,475 ns lcd cl[1] high time t cl2h 80 3,475 ns cl[1] falling to frm transition time t frmd 300 10,425 ns cl[1] falling to m transition time t md ? 10 20 ns cl[2] rising to dd (display data) transition time t ddd ? 10 20 ns figure 12. lcd controller timing measurement cl[2] cl[1] frm m dd [3:0] t cl1d t frmd t cl2h t md t ddd t cl2d t clk t clk_high t clk_low
26 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip jtag parameter symbol min max units tck clock period t clk_per 100 - ns tck clock high time t clk_high 50 - ns tck clock low time t clk_low 50 - ns jtag port setup time t jps 20 - ns jtag port hold time t jph 45 - ns jtag port clock to output t jpco -25ns jtag port high impedance to valid output t jpzx -25ns jtag port valid output to high impedance t jpxz -25ns figure 13. jtag timing measurement tdo tck tdi tms t jph t clk_high t clk_low t jpzx t jpco t jpxz t clk_per t jps
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 27 ep7311 high-performance, low-power system on chip packages 208-pin lqfp package characteristics 208-pin lqfp package specifications note: 1) dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) drawing above does not reflect exact package pin count. 3) before beginning any new design with this device, please contact cirrus logic for the latest package information. 4) for pin locations, please see figure 15 . for pin descriptions see the ep7311 user ? s manual. figure 14. 208-pin lqfp package outline drawing pin 1 indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) bsc 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0 min 7 max 0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 0.45 (0.018) 0.75 (0.030) 0.05 (0.002) 1.00 (0.039) bsc pin 1 pin 208 1.60 (0.063) 0.15 (0.006) ep7311 208-pin lqfp
28 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip 208-pin lqfp pin diagram note: 1. n/c should not be grounded but left as no connects. 2. pin differences between the ep7211 and the ep7311 are bolded. 160 159 158 157 53 54 55 56 57 58 59 60 61 62 63 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 106 107 108 109 110 112 113 114 115 116 117 118 119 120 121 64 65 67 68 69 70 71 72 73 74 75 66 98 99 100 101 102 103 104 122 124 125 126 127 128 129 130 105 131 132 133 134 156 155 154 153 152 151 150 149 148 147 146 145 144 143 140 139 138 137 136 141 142 135 161 162 163 164 165 166 167 168 169 170 171 172 173 174 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 201 202 203 204 205 206 207 208 200 175 176 177 178 179 123 111 ep7311 208-pin lqfp (top view) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 1 nextpwr batok npor vssosc vddosc moscin moscout nureset wakeup a[6] d[6] a[5] d[5] vddio vssio a[4] d[4] a[3] d[3] npwrfl a[2] d[2] a[1] a[0] d[0] vddcore vssio vddio cl[2] cl[1] frm m dd[2] dd[1] dd[0] nsdcs[1] sdqm[3] sdqm[2] vddio vssio sdclk nmwe/nsdwe nmoe/nsdcas ncs[0] ncs[1] ncs[2] ncs[3] d[7] a[7] d[8] a[8] d[9] d[10] a[10] vssio vddio a[11] d[12] a[12] d[13] a[13]\dra[14] d[14] dd[3] d[17] d[15] a[17] /dra[10] ntrst vssio vddio d[18] a[18 /dra[9] d[19] a[19] /dra[8] d[20] vssio a[21] /dra[6] d[22] d[23] a[23] /dra[4] d[24] vssio vddio a[24] /dra[3] halfword a[14]/dra[13] nbatchg a[25]/dra[2] d[25] d[27] a[27]/dra[0] vssio d[28] d[29] d[30] d[31] buz col[0] col[1] tclk vddio col[2] col[3] col[4] col[5] col[6] col[7] fb[0] vssio fb[1] adcout adcclk drive[0] vddio pd[2] vssio vsscore nadccs adcin ssirxda ssirxfr ssitxda ssitxfr vssio ssiclk pd[0]/ledflsh pd[1] pd[3] a[22] /dra[5] pd[4] vddio pd[5] pd[6]/sdqm[0] drive[1] pd[7]/sdqm[1] d[26] a[15] /dra[12] d[16] a[16] /dra[11] ncs[4] vddcore a[26]/dra[1] d[21] tms a[20] /dra[7] smpclk d[11] a[9] d[1] vsscore nsdcs[0 ] sdcke vssio vssio vssio vssio expclk word write/nsdras run/clken exprdy pb[7] pb[6] pb[5] pb[4] pb[3] pb[2] pb[1] vssio tdi vddio tdo pe[2]/clksel nextfiq pa[6] pa[5] pa[4] pa[3] pa[2] pa[1] pa[0] leddrv txd[2] phdin cts rxd[2] dcd dsr rtcout rtcin vssio pa[7] vddio vssio ncs[5] pb[0] txd[1] rxd[1] ntest[1] ntest[0] eint[3] neint[2] neint[1] pe[1]bootsel[1] pe[0]bootsel[0] n/c vssrtc vddrtc figure 15. 208-pin lqfp (low profile quad flat pack) pin diagram nmedchg/nbrom
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 29 ep7311 high-performance, low-power system on chip 208-pin lqfp numeric pin listing table t. 208-pin lqfp numeric pin listing pin no. signal type strength reset state 1ncs[5] o 1 low 2 vddio pad pwr 3 vssio pad gnd 4 expclk i/o 1 5word out 1 low 6 write/nsdras out 1 low 7 run/clken o 1 low 8exprdy i 1 9 txd[2] o 1 high 10 rxd[2] i 11 tdi i with p/u* 12 vssio pad gnd 13 pb[7] i/o 1 input 14 pb[6] i/o 1 input 15 pb[5] i/o 1 input 16 pb[4] i/o 1 input 17 pb[3] i/o 1 input 18 pb[2] i/o 1 input 19 pb[1]/prdy2 i/o 1 input 20 pb[0]/prdy1 i/o 1 input 21 vddio pad pwr 22 tdo o 1 three state 23 pa[7] i/o 1 input 24 pa[6] i/o 1 input 25 pa[5] i/o 1 input 26 pa[4] i/o 1 input 27 pa[3] i/o 1 input 28 pa[2] i/o 1 input 29 pa[1] i/o 1 input 30 pa[0] i/o 1 input 31 leddrv o 1 low 32 txd[1] o 1 high 33 vssio pad gnd 1 high 34 phdin i 35 cts i 36 rxd[1] i 37 dcd i 38 dsr i 39 ntest[1] i with p/u* 40 ntest[0] i with p/u* 41 eint[3] i 42 neint[2] i 43 neint[1] i 44 nextfiq i 45 pe[2]/clksel i/o 1 input 46 pe[1]/ bootsel[1] i/o 1 input 47 pe[0]/ bootsel[0] i/o 1 input 48 vssrtc rtc gnd 49 rtcout o 50 rtcin i 51 vddrtc rtc power 52 n/c 53 pd[7]/sdqm[1] i/o 1 low 54 pd[6]/sdqm[0] i/o 1 low 55 pd[5] i/o 1 low 56 pd[4] i/o 1 low 57 vddio pad pwr 58 tms i with p/u* 59 pd[3] i/o 1 low 60 pd[2] i/o 1 low 61 pd[1] i/o 1 low 62 pd[0]/ledflsh i/o 1 low 63 ssiclk i/o 1 input 64 vssio pad gnd 65 ssitxfr i/o 1 low 66 ssitxda o 1 low 67 ssirxda i 68 ssirxfr i/o input 69 adcin i 70 nadccs o 1 high 71 vsscore core gnd 72 vddcore core pwr 73 vssio pad gnd table t. 208-pin lqfp numeric pin listing (continued) pin no. signal type strength reset state
30 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip 74 vddio pad pwr 75 drive[1] i/o 2 high / low 76 drive[0] i/o 2 high / low 77 adcclk o 1 low 78 adcout o 1 low 79 smpclk o 1 low 80 fb[1] i 81 vssio pad gnd 82 fb[0] i 83 col[7] o 1 high 84 col[6] o 1 high 85 col[5] o 1 high 86 col[4] o 1 high 87 col[3] o 1 high 88 col[2] o 1 high 89 vddio pad pwr 90 tclk i 91 col[1] o 1 high 92 col[0] o 1 high 93 buz o 1 low 94 d[31] i/o 1 low 95 d[30] i/o 1 low 96 d[29] i/o 1 low 97 d[28] i/o 1 low 98 vssio pad gnd 99 a[27]/dra[0] o 2 low 100 d[27] i/o 1 low 101 a[26]/dra[1] o 2 low 102 d[26] i/o 1 low 103 a[25]/dra[2] o 2 low 104 d[25] i/o 1 low 105 halfword o 1 low 106 a[24]/dra[3] o 1 low 107 vddio pad pwr ? 108 vssio pad gnd ? 109 d[24] i/o 1 low 110 a[23]/dra[4] o 1 low table t. 208-pin lqfp numeric pin listing (continued) pin no. signal type strength reset state 111 d[23] i/o 1 low 112 a[22]/dra[5] o 1 low 113 d[22] i/o 1 low 114 a[21]/dra[6] o 1 low 115 d[21] i/o 1 low 116 vssio pad gnd 117 a[20]/dra[7] o 1 low 118 d[20] i/o 1 low 119 a[19]/dra[8] o 1 low 120 d[19] i/o 1 low 121 a[18]/dra[9] o 1 low 122 d[18] i/o 1 low 123 vddio pad pwr 124 vssio pad gnd 125 ntrst i 126 a[17]/dra[10] o 1 low 127 d[17] i/o 1 low 128 a[16]/dra[11] o 1 low 129 d[16] i/o 1 low 130 a[15]/dra[12] o 1 low 131 d[15] i/o 1 low 132 a[14]/dra[13] o 1 low 133 d[14] i/o 1 low 134 a[13]/dra[14] o 1 low 135 d[13] i/o 1 low 136 a[12] o 1 low 137 d[12] i/o 1 low 138 a[11] o 1 low 139 vddio pad pwr 140 vssio pad gnd 141 d[11] i/o 1 low 142 a[10] o 1 low 143 d[10] i/o 1 low 144 a[9] o 1 low 145 d[9] i/o 1 low 146 a[8] o 1 low 147 d[8] i/o 1 low 148 a[7] o 1 low table t. 208-pin lqfp numeric pin listing (continued) pin no. signal type strength reset state
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 31 ep7311 high-performance, low-power system on chip *with p/u ? means with internal pull-up on the pin. 149 vssio pad gnd 150 d[7] i/o 1 low 151 nbatchg i 152 nextpwr i 153 batok i 154 npor i schmitt 155 nmedchg/ nbrom i 156 nureset i schmitt 157 vddosc osc pwr 158 moscin osc 159 moscout osc 160 vssosc osc gnd 161 wakeup i schmitt 162 npwrfl i 163 a[6] o 1 low 164 d[6] i/o 1 low 165 a[5] out 1 low 166 d[5] i/o 1 low 167 vddio pad pwr 168 vssio pad gnd 169 a[4] o 1 low 170 d[4] i/o 1 low 171 a[3] o 2 low 172 d[3] i/o 1 low 173 a[2] o 2 low 174 vssio pad gnd 175 d[2] i/o 1 low 176 a[1] o 2 low 177 d[1] i/o 1 low 178 a[0] o 2 low 179 d[0] i/o 1 low 180 vss core core gnd 181 vdd core core pwr 182 vssio pad gnd 183 vddio pad pwr 184 cl[2] o 1 low 185 cl[1] o 1 low 186 frm o 1 low table t. 208-pin lqfp numeric pin listing (continued) pin no. signal type strength reset state 187 m o 1 low 188 dd[3] i/o 1 low 189 dd[2] i/o 1 low 190 vssio pad gnd 191 dd[1] i/o 1 low 192 dd[0] i/o 1 low 193 nsdcs[1] o 1 high 194 nsdcs[0] o 1 high 195 sdqm[3] i/o 2 low 196 sdqm[2] i/o 2 low 197 vddio pad pwr 198 vssio pad gnd 199 sdcke i/o 2 low 200 sdclk i/o 2 low 201 nmwe/nsdwe o 1 high 202 nmoe/nsdcas o 1 high 203 vssio pad gnd 204 ncs[0] o 1 high 205 ncs[1] o 1 high 206 ncs[2] o 1 high 207 ncs[3] o 1 high 208 ncs[4] o 1 high table t. 208-pin lqfp numeric pin listing (continued) pin no. signal type strength reset state
32 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip 204-ball tfbga package characteristics 204-ball tfbga package specifications figure 16. 204-ball tfbga package ? 0.25~0.35(204x) ? 0.15 m c a b ? 0 . 0 8 m c 0 . 1 5 ( 4 x ) c 0.20~0.30 1.20 max. seating plane 0.36 0.530.05 0.20 c top view bottom view 130.05 130.05 a b c 0.10 c ball diameter : ball pitch : 0.53 0.3 substrate thickness : mold thickness : 0.65 0.36 20 y 0.65 w v u t r p n m l k j h g f e d c b a 19181716151413121110987654321 12.35 0.65 17 19 20 18 16 14 15 12 13 91011 78 456 23 1 c k j h g f e d a b y w v u t r p n m l a1 corner a1 corner 12.35
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 33 ep7311 high-performance, low-power system on chip 204-ball tfbga pinout (top view) 1 2 3 4 5 6 7 8 910111213141516 17 18 19 20 a vddio expclk ncs3 ncs1 nmwe/ nsdwe sdqm2 nsdcs1 dd2 frm cl1 gndcor e d1 a2 d4 a5 npwrfl moscout gndio gndio gndio a b word vddio ncs5 ncs2 nmoe/ nsdcas sdcke nsdcs0 dd1 m cl2 d0 a1 d3 a4 d6 wakeup moscin gndio gndio nureset b c run/ clken exprdy vddio ncs4 ncs0 sdclk sdqm3 dd0 dd3 vddco re a0 d2 a3 d5 a6 gndos c vddosc gndio batok npor c d pb7 rxd2 vddio gndio nbatchg a7 d e pb4 txd2 write/ nsdras nmedchg /nbrom nextpwr d9 e f pb3 pb6 tdi d7 a8 d10 f g pb1/ prdy2 pb2 pb5 d8 a9 d11 g hpa7 tdo pb0/ prdy1 a10 d12 a12 h j pa4 pa5 pa6 a11 d13 a13/ dra14 j k pa1 pa2 vddio d14 a14/ dra13 d15 k l txd1 leddrv pa3 vddio d16 a16/ dra11 l mrxd1 cts pa0 a15/ dra12 a17/ dra10 ntrst m n dsr ntest1 phdin d17 d19 a18/ dra9 n p eint3 neint2 dcd d18 a20/ dra7 d20 p rnextfiq pe2/ clksel ntest0 a19/ dra8 d22 a21/ dra6 r t pe1/ boot sel1 pe0/ boot sel0 neint1 d21 d23 a22/ dra5 t u gndrtcrtcout rtcin half word d24 a23/ dra4 u v vddrtc gndio gndio pd7/ sdqm1 pd4 pd2 ssiclk ssirxda nadccs vddio adcclk col7 col4 tclk buz d29 a26/ dra1 vddio vddio a24/ dra3 v w gndio gndio gndio pd6/sd qm0 tms pd1 ssitxfr ssirxfr gndco re drive1 adcout fb0 col5 col2 col0 d30 a27/ dra0 d26 vddio d25 w y gndio gndio gndio pd5 pd3 pd0/ led flsh ssitxda adcin vddco re drive0 smplck fb1 col6 col3 col1 d31 d28 d27 a25/ dra2 vddio y
34 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip tfbga ball list table u. 204-ball tfbga ball list die pad bond pad package ball signal u2.1 1 b3 ncs5 u2.2 2 y20 vddio u2.3 3 b18 gndio u2.4 4 a2 expclk u2.5 5 b1 word u2.6 6 e3 write/nsdras u2.7 7 c1 run/clken u2.8 8 c2 exprdy u2.9 9 e2 txd2 u2.10 10 d2 rxd2 u2.11 11 f3 tdi u2.12 12 b18 gndio u2.13 13 d1 pb7 u2.14 14 f2 pb6 u2.15 15 g3 pb5 u2.16 16 e1 pb4 u2.17 17 f1 pb3 u2.18 18 g2 pb2 u2.19 19 g1 pb1/prdy2 u2.20 20 h3 pb0/prdy1 u2.21 21 y20 vddio u2.22 22 h2 tdo u2.23 23 h1 pa7 u2.24 24 j3 pa6 u2.25 25 j2 pa5 u2.26 26 j1 pa4 u2.27 27 l3 pa3 u2.28 28 k2 pa2 u2.29 29 k1 pa1 u2.30 30 m3 pa0 u2.31 31 l2 leddrv u2.32 32 l1 txd1 u2.33 33 b18 gndio u2.34 34 n3 phdin u2.35 35 m2 cts u2.36 36 m1 rxd1 u2.37 37 p3 dcd u2.38 38 n1 dsr u2.39 39 n2 ntest1 u2.40 40 r3 ntest0 u2.41 41 p1 eint3 u2.42 42 p2 neint2 u2.43 43 t3 neint1 u2.44 44 r1 nextfiq u2.45 45 r2 pe2/clksel u2.46 46 t1 pe1/bootsel1 u2.47 47 t2 pe0/bootsel0 u2.48 48 u1 gndrtc u2.49 49 u2 rtcout u2.50 50 u3 rtcin u2.51 51 v1 vddrtc u2.53 52 v4 pd7/sdqm1 u2.54 53 w4 pd6/sdqm0 u2.55 54 y4 pd5 u2.56 55 v5 pd4 u2.57 56 l18 vddio u2.58 57 w5 tms u2.59 58 y5 pd3 u2.60 59 v6 pd2 u2.61 60 w6 pd1 u2.62 61 y6 pd0/ledflsh u2.63 62 v7 ssiclk u2.64 63 d18 gndio u2.65 64 w7 ssitxfr u2.66 65 y7 ssitxda u2.67 66 v8 ssirxda u2.68 67 w8 ssirxfr u2.69 68 y8 adcin u2.70 69 v9 nadccs u2.71 70 w9 gndcore u2.72 71 y9 vddcore u2.73 72 w3 gndio u2.74 73 v10 vddio u2.75 74 l18 vddio u2.76 75 w10 drive1 u2.77 76 y10 drive0 u2.78 77 v11 adcclk table u. 204-ball tfbga ball list (continued) die pad bond pad package ball signal
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 35 ep7311 high-performance, low-power system on chip u2.79 78 w11 adcout u2.80 79 y11 smplck u2.81 80 y12 fb1 u2.82 81 y3 gndio u2.83 82 w12 fb0 u2.84 83 v12 col7 u2.85 84 y13 col6 u2.86 85 w13 col5 u2.87 86 v13 col4 u2.88 87 y14 col3 u2.89 88 w14 col2 u2.90 89 a1 vddio u2.91 90 v14 tclk u2.92 91 y15 col1 u2.93 92 w15 col0 u2.94 93 v15 buz u2.95 94 y16 d31 u2.96 95 w16 d30 u2.97 96 v16 d29 u2.98 97 y17 d28 u2.99 98 y3 gndio u2.100 99 w17 a27/dra0 u2.101 100 y18 d27 u2.102 101 v17 a26/dra1 u2.103 102 w18 d26 u2.104 103 y19 a25/dra2 u2.105 104 w20 d25 u2.106 105 u18 halfword u2.107 106 v20 a24/dra3 u2.108 107 a1 vddio u2.109 108 y3 gndio u2.110 109 u19 d24 u2.111 110 u20 a23/dra4 u2.112 111 t19 d23 u2.113 112 t20 a22/dra5 u2.114 113 r19 d22 u2.115 114 r20 a21/dra6 u2.116 115 t18 d21 u2.117 116 y3 gndio table u. 204-ball tfbga ball list (continued) die pad bond pad package ball signal u2.118 117 p19 a20/dra7 u2.119 118 p20 d20 u2.120 119 r18 a19/dra8 u2.121 120 n19 d19 u2.122 121 n20 a18/dra9 u2.123 122 p18 d18 u2.124 123 a1 vddio u2.125 124 y3 gndio u2.126 125 m20 ntrst u2.127 126 m19 a17/dra10 u2.128 127 n18 d17 u2.129 128 l20 a16/dra11 u2.130 129 l19 d16 u2.131 130 m18 a15/dra12 u2.132 131 k20 d15 u2.133 132 k19 a14/dra13 u2.134 133 k18 d14 u2.135 134 j20 a13/dra14 u2.136 135 j19 d13 u2.137 136 h20 a12 u2.138 137 h19 d12 u2.139 138 j18 a11 u2.140 139 k3 vddio u2.141 140 y3 gndio u2.142 141 g20 d11 u2.143 142 h18 a10 u2.144 143 f20 d10 u2.145 144 g19 a9 u2.146 145 e20 d9 u2.147 146 f19 a8 u2.148 147 g18 d8 u2.149 148 d20 a7 u2.150 149 y3 gndio u2.151 150 f18 d7 u2.152 151 d19 nbatchg u2.153 152 e19 nextpwr u2.154 153 c19 batok u2.155 154 c20 npor u2.156 155 e18 nmedchg/nbrom table u. 204-ball tfbga ball list (continued) die pad bond pad package ball signal
36 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip u2.157 156 b20 nureset u2.158 157 c17 vddosc u2.159 158 b17 moscin u2.160 159 a17 moscout u2.161 160 c16 gndosc u2.162 161 b16 wakeup u2.163 162 a16 npwrfl u2.164 163 c15 a6 u2.165 164 b15 d6 u2.166 165 a15 a5 u2.167 166 c14 d5 u2.168 167 a1 vddio u2.169 168 y3 gndio u2.170 169 b14 a4 u2.171 170 a14 d4 u2.172 171 c13 a3 u2.173 172 b13 d3 u2.174 173 a13 a2 u2.175 174 y3 gndio u2.176 175 c12 d2 u2.177 176 b12 a1 u2.178 177 a12 d1 u2.179 178 c11 a0 u2.180 179 b11 d0 u2.181 180 a11 gndcore u2.182 181 c10 vddcore u2.183 182 y3 gndio u2.184 183 y20 vddio u2.185 184 b10 cl2 u2.186 185 a10 cl1 u2.187 186 a9 frm u2.188 187 b9 m u2.189 188 c9 dd3 u2.190 189 a8 dd2 u2.191 190 y3 gndio u2.192 191 b8 dd1 u2.193 192 c8 dd0 u2.194 193 a7 nsdcs1 u2.195 194 b7 nsdcs0 table u. 204-ball tfbga ball list (continued) die pad bond pad package ball signal u2.196 195 c7 sdqm3 u2.197 196 a6 sdqm2 u2.198 197 v18 vddio u2.199 198 b18 gndio u2.200 199 b6 sdcke u2.201 200 c6 sdclk u2.202 201 a5 nmwe/nsdwe u2.203 202 b5 nmoe/nsdcas u2.204 203 b18 gndio u2.205 204 c5 ncs0 u2.206 205 a4 ncs1 u2.207 206 b4 ncs2 u2.208 207 a3 ncs3 u2.209 208 c4 ncs4 a1 vddio b2 vddio c3 vddio d3 vddio k3 vddio l18 vddio v18 vddio v19 vddio w19 vddio y20 vddio a18 gndio a19 gndio a20 gndio b18 gndio b19 gndio c18 gndio d18 gndio v2 gndio v3 gndio w1 gndio w2 gndio w3 gndio y1 gndio y2 gndio y3 gndio table u. 204-ball tfbga ball list (continued) die pad bond pad package ball signal
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 37 ep7311 high-performance, low-power system on chip 256-ball pbga package characteristics 256-ball pbga package specifications figure 17. 256-ball pbga package note: 1) for pin locations see ta bl e v . 2) dimensions are in millimeters (inches), and controlling dimension is millimeter 3) before beginning any new ep7311 design, contact cirrus logic for the latest package information. top view 17.00 (0.669) 15.00 (0.590) side view bottom view a b c d e f g h j k l m n p r t 1.00 (0.040) pin 1 indicator pin 1 corner pin 1 corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15.00 (0.590) 2 layer 17.00 (0.669) 17.00 (0.669) 1.00 (0.040) 1.00 (0.040) 1.00 (0.040) 30 typ ref ref 0.50 3 places 0.85 (0.034) 0.05 (.002) 0.40 (0.016) 0.05 (.002) 0.36 (0.014) 17.00 (0.669) r d1 e1 d e 0.20 (.008) 0.20 (.008) 0.20 (.008) 0.20 (.008) 0.09 (0.004) jedec #: mo-151 ball diameter: 0.50 mm 0.10 mm 17 17 1.61 mm body
38 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip 256-ball pbga pinout (top view) 1 2 3 4 5 6 7 8 910111213141516 a vddio ncs[4] ncs[1] sdclk sdqm[3] dd[1] m vddio d[0] d[2] a[3] vddio a[6] moscout vddosc vssio a b ncs[5] vddio ncs[3] nmoe/ nsdcas vddio nsdcs[1] dd[2] cl[1] vddcore d[1] a[2] a[4] a[5] wakeup vddio nureset b c vddio expclk vssio vddio vssio vssio vssio vddio vssio vssio vssio vddio vssio vssio npor nextpwr c d write/ nsdras exprdy vssio vddio ncs[2] nmwe/ nsdwe nsdcs[0] cl[2] vssrtc d[4] npwrfl moscin vddio vssio d[7] d[8] d e rxd[2] pb[7] tdi word vssio ncs[0] sdqm[2] frm a[0] d[5] vssosc vssio nmedchg/ nbrom vddio d[9] d[10] e f pb[5] pb[3] vssio txd[2] run/ clken vssio sdcke dd[3] a[1] d[6] vssrtc batok nbatchg vssio d[11] vddio f g pb[1] vddio tdo pb[4] pb[6] vssrtc vssrtc dd[0] d[3] vssrtc a[7] a[8] a[9] vssio d[12] d[13] g h pa[7] pa[5] vssio pa[4] pa[6] pb[0] pb[2] vssrtc vssrtc a[10] a[11] a[12] a[13]/ dra[14] vssio d[14] d[15] h j pa[3] pa[1] vssio pa[2] pa[0] txd[1] cts vssrtc vssrtc a[17]/ dra[10] a[16]/ dra[11] a[15]/ dra[12] a[14]/ dra[13] ntrst d[16] d[17] j k leddrv phdin vssio dcd ntest[1] eint[3] vssrtc adcin col[4] tclk d[20] d[19] d[18] vssio vddio vddio k l rxd[1] dsr vddio neint[1] pe[2]/ clksel vssrtc pd[0]/ ledflsh vssrtc col[6] d[31] vssrtc a[22]/ dra[5] a[21]/ dra[6] vssio a[18]/ dra[9] a[19]/ dra[8] l m ntest[0] neint[2] vddio pe[0]/ bootsel[0] tms vddio ssitxfr drive[1] fb[0] col[0] d[27] vssio a[23]/ dra[4] vddio a[20]/ dra[7] d[21] m n nextfiq pe[1]/ bootsel[1] vssio vddio pd[5] pd[2] ssirxda adcclk smpclk col[2] d[29] d[26] halfword vssio d[22] d[23] n p vssrtc rtcout vssio vssio vddio vssio vssio vddio vssio vddio vssio vssio vddio vssio d[24] vddio p r rtcin vddio pd[4] pd[1] ssitxda nadccs vddio adcout col[7] col[3] col[1] d[30] a[27]/ dra[0] a[25]/ dra[2] vddio a[24]\ dra[3] r t vddrtc pd[7]/ sdqm[1] pd[6]/ sdqm[0] pd[3] ssiclk ssirxfr vddcore drive[0] fb[1] col[5] vddio buz d[28] a[26]/ dra[1] d[25] vssio t
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 39 ep7311 high-performance, low-power system on chip 256-ball pbga ball listing the list is ordered by ball location. table v. 256-ball pbga ball listing ball location name type description a1 vddio pad power digital i/o power, 3.3v a2 ncs[4] o chip select out a3 ncs[1] o chip select out a4 sdclk o sdram clock out a5 sdqm[3] o sdram byte lane mask a6 dd[1] o lcd serial display data a7 m o lcd ac bias drive a8 vddio pad power digital i/o power, 3.3v a9 d[0] i/o data i/o a10 d[2] i/o data i/o a11 a[3] o system byte address a12 vddio pad power digital i/o power, 3.3v a13 a[6] o system byte address a14 moscout o main oscillator out a15 vddosc oscillator power oscillator power in, 2.5v a16 vssio pad ground i/o ground b1 ncs[5] o chip select out b2 vddio pad power i/o ground b3 ncs[3] o chip select out b4 nmoe/nsdcas o rom, expansion op enable/sdram cas control signal b5 vddio pad power digital i/o power, 3.3v b6 nsdcs[1] o sdram chip select out b7 dd[2] o lcd serial display data b8 cl[1] o lcd line clock b9 vddcore core power digital core power, 2.5v b10 d[1] i/o data i/o b11 a[2] o system byte address b12 a[4] o system byte address b13 a[5] o system byte address b14 wakeup i system wake up input b15 vddio pad power digital i/o power, 3.3v b16 nureset i user reset input c1 vddio pad power digital i/o power, 3.3v c2 expclk i expansion clock input c3 vssio pad ground i/o ground c4 vddio pad power digital i/o power, 3.3v c5 vssio pad ground i/o ground c6 vssio pad ground i/o ground c7 vssio pad ground i/o ground c8 vddio pad power digital i/o power, 3.3v c9 vssio pad ground i/o ground c10 vssio pad ground i/o ground c11 vssio pad ground i/o ground c12 vddio pad power digital i/o power, 3.3v c13 vssio pad ground i/o ground c14 vssio pad ground i/o ground c15 npor i power-on reset input c16 nextpwr i external power supply sense input d1 write/nsdras o transfer direction / sdram ras signal output d2 exprdy i expansion port ready input d3 vssio pad ground i/o ground d4 vddio pad power digital i/o power, 3.3v d5 ncs[2] o chip select out d6 nmwe/nsdwe o rom, expansion write enable/ sdram write enable control signal d7 nsdcs[0] o sdram chip select out d8 cl[2] o lcd pixel clock out d9 vssrtc core ground real time clock ground d10 d[4] i/o data i/o d11 npwrfl i power fail sense input d12 moscin i main oscillator input d13 vddio pad power digital i/o power, 3.3v d14 vssio pad ground i/o ground d15 d[7] i/o data i/o d16 d[8] i/o data i/o e1 rxd[2] i uart 2 receive data input e2 pb[7] i gpio port b e3 tdi i jtag data input e4 word o word access select output e5 vssio pad ground i/o ground e6 ncs[0] o chip select out e7 sdqm[2] o sdram byte lane mask e8 frm o lcd frame synchronization pulse e9 a[0] o system byte address e10 d[5] i/o data i/o e11 vssosc oscillator ground pll ground e12 vssio pad ground i/o ground e13 nmedchg/nbrom i media change interrupt input / internal rom boot enable e14 vddio pad power digital i/o power, 3.3v e15 d[9] i/o data i/o e16 d[10] i/o data i/o f1 pb[5] i gpio port b f2 pb[3] i gpio port b f3 vssio pad ground i/o ground f4 txd[2] o uart 2 transmit data output f5 run/clken o run output / clock enable output f6 vssio pad ground i/o ground table v. 256-ball pbga ball listing (continued) ball location name type description
40 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip f7 sdcke o sdram clock enable output f8 dd[3] o lcd serial display data f9 a[1] o system byte address f10 d[6] i/o data i/o f11 vssrtc rtc ground real time clock ground f12 batok i battery ok input f13 nbatchg i battery changed sense input f14 vssio pad ground i/o ground f15 d[11] i/o data i/o f16 vddio pad power digital i/o power, 3.3v g1 pb[1] i gpio port b g2 vddio pad power digital i/o power, 3.3v g3 tdo o jtag data out g4 pb[4] i gpio port b g5 pb[6] i gpio port b g6 vssrtc core ground real time clock ground g7 vssrtc rtc ground real time clock ground g8 dd[0] o lcd serial display data g9 d[3] i/o data i/o g10 vssrtc rtc ground real time clock ground g11 a[7] o system byte address g12 a[8] o system byte address g13 a[9] o system byte address g14 vssio pad ground i/o ground g15 d[12] i/o data i/o g16 d[13] i/o data i/o h1 pa[7] i gpio port a h2 pa[5] i gpio port a h3 vssio pad ground i/o ground h4 pa[4] i gpio port a h5 pa[6] i gpio port a h6 pb[0] i gpio port b h7 pb[2] i gpio port b h8 vssrtc rtc ground real time clock ground h9 vssrtc rtc ground real time clock ground h10 a[10] o system byte address h11 a[11] o system byte address h12 a[12] o system byte address h13 a[13]/dra[14] o system byte address / sdram address h14 vssio pad ground i/o ground h15 d[14] i/o data i/o h16 d[15] i/o data i/o j1 pa[3] i gpio port a j2 pa[1] i gpio port a j3 vssio pad ground i/o ground j4 pa[2] i gpio port a j5 pa[0] i gpio port a j6 txd[1] o uart 1 transmit data out table v. 256-ball pbga ball listing (continued) ball location name type description j7 cts i uart 1 clear to send input j8 vssrtc rtc ground real time clock ground j9 vssrtc rtc ground real time clock ground j10 a[17]/dra[10] o system byte address / sdram address j11 a[16]/dra[11] o system byte address / sdram address j12 a[15]/dra[12] o system byte address / sdram address j13 a[14]/dra[13] o system byte address / sdram address j14 ntrst i jtag async reset input j15 d[16] i/o data i/o j16 d[17] i/o data i/o k1 leddrv o ir led drivet k2 phdin i photodiode input k3 vssio pad ground i/o ground k4 dcd i uart 1 data carrier detect k5 ntest[1] i test mode select input k6 eint[3] i external interrupt k7 vssrtc rtc ground real time clock ground k8 adcin i ssi1 adc serial input k9 col[4] o keyboard scanner column drive k10 tclk i jtag clock k11 d[20] i/o data i/o k12 d[19] i/o data i/o k13 d[18] i/o data i/o k14 vssio pad ground i/o ground k15 vddio pad power digital i/o power, 3.3v k16 vddio pad power digital i/o power, 3.3v l1 rxd[1] i uart 1 receive data input l2 dsr i uart 1 data set ready input l3 vddio pad power digital i/o power, 3.3v l4 neint[1] i external interrupt input l5 pe[2]/clksel i gpio port e / clock input mode select l6 vssrtc rtc ground real time clock ground l7 pd[0]/ledflsh i/o gpio port d / led blinker output l8 vssrtc core ground real time clock ground l9 col[6] o keyboard scanner column drive l10 d[31] i/o data i/o l11 vssrtc rtc ground real time clock ground l12 a[22]/dra[5] o system byte address / sdram address l13 a[21]/dra[6] o system byte address / sdram address l14 vssio pad ground i/o ground l15 a[18]/dra[9] o system byte address / sdram address l16 a[19]/dra[8] o system byte address / sdram address m1 ntest[0] i test mode select input m2 neint[2] i external interrupt input m3 vddio pad power digital i/o power, 3.3v m4 pe[0]/bootsel[0] i gpio port e / boot mode select m5 tms i jtag mode select m6 vddio pad power digital i/o power, 3.3v table v. 256-ball pbga ball listing (continued) ball location name type description
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 41 ep7311 high-performance, low-power system on chip m7 ssitxfr i/o mcp/codec/ssi2 frame sync m8 drive[1] i/o pwm drive output m9 fb[0] i pwm feedback input m10 col[0] o keyboard scanner column drive m11 d[27] i/o data i/o m12 vssio pad ground i/o ground m13 a[23]/dra[4] o system byte address / sdram address m14 vddio pad power digital i/o power, 3.3v m15 a[20]/dra[7] o system byte address / sdram address m16 d[21] i/o data i/o n1 nextfiq i external fast interrupt input n2 pe[1]/bootsel[1] i gpio port e / boot mode select n3 vssio pad ground i/o ground n4 vddio pad power digital i/o power, 3.3v n5 pd[5] i/o gpio port d n6 pd[2] i/o gpio port d n7 ssirxda i/o mcp/codec/ssi2 serial data input n8 adcclk o ssi1 adc serial clock n9 smpclk o ssi1 adc sample clock n10 col[2] o keyboard scanner column drive n11 d[29] i/o data i/o n12 d[26] i/o data i/o n13 halfword o halfword access select output n14 vssio pad ground i/o ground n15 d[22] i/o data i/o n16 d[23] i/o data i/o p1 vssrtc rtc ground real time clock ground p2 rtcout o real time clock oscillator output p3 vssio pad ground i/o ground p4 vssio pad ground i/o ground p5 vddio pad power digital i/o power, 3.3v p6 vssio pad ground i/o ground p7 vssio pad ground i/o ground p8 vddio pad power digital i/o power, 3.3v p9 vssio pad ground i/o ground p10 vddio pad power digital i/o power, 3.3v p11 vssio pad ground i/o ground p12 vssio pad ground i/o ground p13 vddio pad power digital i/o power p14 vssio pad ground i/o ground p15 d[24] i/o data i/o p16 vddio pad power digital i/o power, 3.3v r1 rtcin i/o real time clock oscillator input r2 vddio pad power digital i/o power, 3.3v r3 pd[4] i/o gpio port d r4 pd[1] i/o gpio port d r5 ssitxda o mcp/codec/ssi2 serial data output r6 nadccs o ssi1 adc chip select table v. 256-ball pbga ball listing (continued) ball location name type description r7 vddio pad power digital i/o power, 3.3v r8 adcout o ssi1 adc serial data output r9 col[7] o keyboard scanner column drive r10 col[3] o keyboard scanner column drive r11 col[1] o keyboard scanner column drive r12 d[30] i/o data i/o r13 a[27]/dra[0] o system byte address / sdram address r14 a[25]/dra[2] o system byte address / sdram address r15 vddio pad power digital i/o power, 3.3v r16 a[24]/dra[3] o system byte address / sdram address t1 vddrtc rtc power real time clock power, 2.5v t2 pd[7]/sdqm[1] i/o gpio port d / sdram byte lane mask t3 pd[6]/sdqm[0] i/o gpio port d / sdram byte lane mask t4 pd[3] i/o gpio port d t5 ssiclk i/o mcp/codec/ssi2 serial clock t6 ssirxfr ? mcp/codec/ssi2 frame sync t7 vddcore core power core power, 2.5v t8 drive[0] i/o pwm drive output t9 fb[1] i pwm feedback input t10 col[5] o keyboard scanner column drive t11 vddio pad power digital i/o power, 3.3v t12 buz o buzzer drive output t13 d[28] i/o data i/o t14 a[26]/dra[1] o system byte address / sdram address t15 d[25] i/o data i/o t16 vssio pad ground i/o ground table v. 256-ball pbga ball listing (continued) ball location name type description
42 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip jtag boundary scan signal ordering table w. jtag boundary scan signal ordering lqfp pin no. tfbga ball pbga ball signal type position 1b3b1 ncs[5] o 1 4 a2 c2 expclk i/o 3 5b1e4 word o 6 6 e3 d1 write/nsdras o 8 7 c1 f5 run/clken o 10 8 c2 d2 exprdy i 13 9e2f4 txd2 o 14 10 d2 e1 rxd2 i 16 13 f3 e2 pb[7] i/o 17 14 d1 g5 pb[6] i/o 20 15 f2 f1 pb[5] i/o 23 16 g3 g4 pb[4] i/o 26 17 e1 f2 pb[3] i/o 29 18 f1 h7 pb[2] i/o 32 19 g2 g1 pb[1]/prdy2 i/o 35 20 g1 h6 pb[0]/prdy1 i/o 38 23 h3 h1 pa[7] i/o 41 24 h1 h5 pa[6] i/o 44 25 j3 h2 pa[5] i/o 47 26 j2 h4 pa[4] i/o 50 27 j1 j1 pa[3] i/o 53 28 l3 j4 pa[2] i/o 56 29 k2 j2 pa[1] i/o 59 30 k1 j5 pa[0] i/o 62 31 m3 k1 leddrv o 65 32 l2 j6 txd1 o 67 34 l1 k2 phdin i 69 35 n3 j7 cts i 70 36 m2 l1 rxd1 i 71 37 m1 k4 dcd i 72 38 p3 l2 dsr i 73 39 n1 k5 ntest1 i 74 40 n2 m1 ntest0 i 75 41 r3 k6 eint3 i 76 42 p1 m2 neint2 i 77 43 p2 l4 neint1 i 78
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 43 ep7311 high-performance, low-power system on chip 44 t3 n1 nextfiq i 79 45 r1 l5 pe[2]/clksel i/o 80 46 r2 n2 pe[1]/bootsel1 i/o 83 47 t1 m4 pe[0]/bootsel0 i/o 86 53 t2 t2 pd[7]/sdqm[1] i/o 89 54 v4 t3 pd[6/sdqm[0]] i/o 92 55 w4 n5 pd[5] i/o 95 56 y4 r3 pd[4] i/o 98 59 v5 t4 pd[3] i/o 101 60 w5 n6 pd[2] i/o 104 61 y5 r4 pd[1] i/o 107 62 v6 l7 pd[0]/ledflsh o 110 68 w6 t6 ssirxfr i/o 122 69 y6 k8 adcin i 125 70 w8 r6 nadccs o 126 75 y8 m8 drive1 i/o 128 76 v9 t8 drive0 i/o 131 77 w10 n8 adcclk o 134 78 y10 r8 adcout o 136 79 v11 n9 smpclk o 138 80 w11 t9 fb1 i 140 82 y11 m9 fb0 i 141 83 y12 r9 col7 o 142 84 w12 l9 col6 o 144 85 v12 t10 col5 o 146 86 y13 k9 col4 o 148 87 w13 r10 col3 o 150 88 v13 n10 col2 o 152 91 y14 r11 col1 o 154 92 w14 m10 col0 o 156 93 a1 t12 buz o 158 94 v14 l10 d[31] i/o 160 95 y15 r12 d[30] i/o 163 96 w15 n11 d[29] i/o 166 97 v15 t13 d[28] i/o 169 99 y16 r13 a[27]/dra[0] out 172 100 w16 m11 d[27] i/o 174 101 v16 t14 a[26]/dra[1] o 177 table w. jtag boundary scan signal ordering (continued) lqfp pin no. tfbga ball pbga ball signal type position
44 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip 102 y17 n12 d[26] i/o 179 103 w17 r14 a[25]/dra[2] o 182 104 y18 t15 d[25] i/o 184 105 v17 n13 halfword o 187 106 w18 r16 a[24]/dra[3] o 189 109 y19 p15 d[24] i/o 191 110 w20 m13 a[23]/dra[4] o 194 111 u18 n16 d[23] i/o 196 112 v20 l12 a[22]/dra[5] o 199 113 u19 n15 d[22] i/o 201 114 u20 l13 a[21]/dra[6] o 204 115 t19 m16 d[21] i/o 206 117 t20 m15 a[20]/dra[7] o 209 118 r19 k11 d[20] i/o 211 119 r20 l16 a[19]/dra[8] o 214 120 t18 k12 d[19] i/o 216 121 p19 l15 a[18]/dra[9] o 219 122 p20 k13 d[18] i/o 221 126 r18 j10 a[17]/dra[10] o 224 127 n19 j16 d[17] i/o 226 128 n20 j11 a[16]/dra[11] o 229 129 p18 j15 d[16] i/o 231 130 m19 j12 a[15]/dra[12] o 234 131 n18 h16 d[15] i/o 236 132 l20 j13 a[14]/dra[13] o 239 133 l19 h15 d[14] i/o 241 134 m18 h13 a[13]/dra[14] o 244 135 k20 g16 d[13] i/o 246 136 k19 h12 a[12] o 249 137 k18 g15 d[12] i/o 251 138 j20 h11 a[11] o 254 141 j19 f15 d[11] i/o 256 142 h20 h10 a[10] o 259 143 h19 e16 d[10] i/o 261 144 j18 g13 a[9] o 264 145 k3 e15 d[9] i/o 266 146 y3 g12 a[8] o 269 147 g20 d16 d[8] i/o 271 table w. jtag boundary scan signal ordering (continued) lqfp pin no. tfbga ball pbga ball signal type position
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 45 ep7311 high-performance, low-power system on chip 148 h18 g11 a[7] o 274 150 f20 d15 d[7] i/o 276 151 g19 f13 nbatchg i 279 152 e20 c16 nextpwr i 280 153 f19 f12 batok i 281 154 g18 c15 npor i 282 155 d20 e13 nmedchg/nbrom i 283 156 f18 b16 nureset i 284 161 d19 b14 wakeup i 285 162 e19 d11 npwrfl i 286 163 c19 a13 a[6] o 287 164 c20 f10 d[6] i/o 289 165 e18 b13 a[5] o 292 166 b20 e10 d[5] i/o 294 169 b16 b12 a[4] o 297 170 a16 d10 d[4] i/o 299 171 c15 a11 a[3] o 302 172 b15 g9 d[3] i/o 304 173 a15 b11 a[2] o 307 175 c14 a10 d[2] i/o 309 176 b14 f9 a[1] o 312 177 a14 b10 d[1] i/o 314 178 c13 e9 a[0] o 317 179 b13 a9 d[0] i/o 319 184 a13 d8 cl2 o 322 185 c12 b8 cl1 o 324 186 b12 e8 frm o 326 187 a12 a7 m o 328 188 c11 f8 dd[3] i/o 330 189 b11 b7 dd[2] i/o 333 191 b10 a6 dd[1] i/o 336 192 a10 g8 dd[0] i/o 339 193 a9 b6 nsdcs[1] o 342 194 b9 d7 nsdcs[0] o 344 195 c9 a5 sdqm[3] i/o 346 196 a8 e7 sdqm[2] i/o 349 199 b8 f7 sdcke i/o 352 200 c8 a4 sdclk i/o 355 table w. jtag boundary scan signal ordering (continued) lqfp pin no. tfbga ball pbga ball signal type position
46 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip 1) see ep7311 users ? manual for pin naming / functionality. 2) for each pad, the jtag connection ordering is input, output, then enable as applicable. 201 a7 d6 nmwe/nsdwe o 358 202 b7 b4 nmoe/nsdcas o 360 204 c7 e6 ncs[0] o 362 205 a6 a3 ncs[1] o 364 206 b6 d5 ncs[2] o 366 207 c6 b3 ncs[3] o 368 208 a5 a2 ncs[4] o 370 table w. jtag boundary scan signal ordering (continued) lqfp pin no. tfbga ball pbga ball signal type position
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 47 ep7311 high-performance, low-power system on chip conventions this section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. acronyms and abbreviations table x lists abbreviations and acronyms used in this data sheet. units of measurement table x. acronyms and abbreviations acronym/ abbreviation definition a/d analog-to-digital adc analog-to-digital converter codec coder / decoder d/a digital-to-analog dma direct-memory access epb embedded peripheral bus fcs frame check sequence fifo first in / first out fiq fast interrupt request gpio general purpose i/o ict in circuit test ir infrared irq standard interrupt request irda infrared data association jtag joint test action group lcd liquid crystal display led light-emitting diode lqfp low profile quad flat pack lsb least significant bit mips millions of instructions per second mmu memory management unit msb most significant bit pbga plastic ball grid array pcb printed circuit board pda personal digital assistant pll phase locked loop p/u pull-up resistor risc reduced instruction set computer rtc real-time clock sir slow (9600 ? 115.2 kbps) infrared sram static random access memory ssi synchronous serial interface tap test access port tlb translation lookaside buffer uart universal asynchronous receiver table y. unit of measurement symbol unit of measure c degree celsius fs sample frequency hz hertz (cycle per second) kbps kilobits per second kb kilobyte (1,024 bytes) khz kilohertz k ? kilohm mbps megabits (1,048,576 bits) per second mb megabyte (1,048,576 bytes) mbps megabytes per second mhz megahertz (1,000 kilohertz) a microampere fmicrofarad wmicrowatt s microsecond (1,000 nanoseconds) ma milliampere mw milliwatt ms millisecond (1,000 microseconds) ns nanosecond vvolt wwatt table x. acronyms and abbreviations (continued) acronym/ abbreviation definition
48 ? copyright 2001 cirrus logic (all rights reserved) ds506pp1 ep7311 high-performance, low-power system on chip general conventions hexadecimal numbers are presented with all letters in uppercase and a lowercase ? h ? appended or with a 0x at the beginning. for example, 0x14 and 03cah are hexadecimal numbers. binary numbers are enclosed in single quotation marks when in text (for example, ? 11 ? designates a binary number). numbers not indicated by an ? h ? , 0x or quotation marks are decimal. registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, codr[7:0]), and are described in the ep7311 user ? s manual. the use of ? tbd ? indicates values that are ? to be determined, ? ? n/a ? designates ? not available, ? and ? n/c ? indicates a pin that is a ? no connect. ? pin description conventions abbreviations used for signal directions are listed in ta ble z. table z. pin description conventions abbreviation direction i input ooutput i/o input or output
ds506pp1 ? copyright 2001 cirrus logic (all rights reserved) 49 ep7311 high-performance, low-power system on chip ordering information the order number for the device is: note: contact cirrus logic for up-to-date information on revisions. go to the cirrus logic internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. ep7312 ? cv ? c product line: embedded processor part number temperature range: package type: v = low profile quad flat pack b = plastic ball grid array (17 mm x 17 mm) revision ? r = reduced ball grid array (13 mm x 13 mm) c = commercial e = extended operating version i = industrial operating version

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